1. Field of the Invention
The invention pertains to the field of integrated circuits. More particularly, the invention pertains to programmable logic integrated circuit devices adapted to enter a low-power mode.
2. Description of Related Art
Programmable logic integrated circuit devices (PLDs) are known in the art. A PLD comprises any number of programmable elements and their associated control elements. Programmable elements are building blocks used to construct the various design elements of a complete design specified by the end user. Examples of programmable elements are logic modules capable of implementing a variety of Boolean functions, flip/flops, routing interconnect wires, input buffers, output buffers, and complex functional blocks such as static random access memories (SRAMs) and digital multipliers. Often a programmable element requires multiple control elements to specify its use and function. The programmable elements are initially uncommitted until a control data structure (which may also be called control data or programming data or bit stream data) is stored in the control elements.
The control elements may be thought of as binary bits having values such as on/off, conductive/non-conductive, true/false, or logic-1/logic-0 depending on the context. The control elements vary according to the technology employed and their mode of data storage may be either volatile or non-volatile. Volatile control elements, such as SRAM bits, lose their programming data when the PLD power supply is disconnected, disabled or turned off. Non-volatile control elements, such as antifuses and floating gate transistors, do not lose their programming data when the PLD power supply is removed. Some control elements, such as antifuses, can be programmed only one time and cannot be erased. Other control elements, such as SRAM bits and floating gate transistors, can have their programming data erased and may be reprogrammed many times. The detailed circuit implementation of the programmable elements can vary greatly and must be appropriate for the type of control element used.
Like most integrated circuits, PLDs typically have an input/output (I/O) ring surrounding a central core, though other approaches are possible. The I/O ring contains the input and output buffers that interface to circuits external to the PLD as well as the power supply and ground connections. Some of the input and output buffers are typically dedicated to control functions. Others are programmable elements which can be part of an end user's complete design. It is common for the programmable element inputs and outputs (also called user inputs or user input buffers and user outputs or user output buffers) to pair equal numbers of input buffers and output buffers together to form input/output buffers (also called I/O buffers or user I/O buffers or user I/Os or sometimes simply I/Os). In some PLDs, one or more of the inputs, outputs, or I/Os can be shared between user design functions and control functions.
Like most integrated circuits, PLDs are typically sold inside a protective enclosure called a package, though other approaches may be used. The package protects the PLD from physical damage and chemical contamination as well as providing a reliable means for safely mounting the PLD on a printed circuit board in the end user's electronic system (sometimes known as an application). The package has a number of external conductive leads (sometimes called pins). The mounting process typically involves soldering the pins to conductive traces disposed on the printed circuit board. In some applications where a less permanent interface is desired, the package can be placed in a socket mounted on the printed circuit board which holds the PLD securely in place and indirectly couples the pins to the conductive traces disposed on the printed circuit board.
Typically the PLD is glued into the center of the floor of a cavity inside the package. The periphery of the cavity is typically lined with bond posts conductively coupled to the external pins. The PLD typically has bond pads located in the I/O ring placed to allow bond wires to couple the bond pads to the bond posts. After the bond wires are placed, the cavity is sealed in a manner appropriate for the type of package used. Thus the PLD is protected while the various inputs, outputs, I/Os, power, and ground connections are conductively coupled to the appropriate package conductive leads and ultimately to the appropriate conductive traces on the printed circuit board in the electronic system.
In a pure PLD, the central core contains a programmable logic block comprising the majority of the programmable elements and control elements. The programmable logic block also typically contains a variety of control circuits. There may be other control circuits present either inside the central core or inside the I/O ring or divided between the central core and the I/O ring. This control circuitry handles various tasks such as testing the PLD functionality, programming the control elements, or transitioning the PLD from one mode of operation to another. In a hybrid PLD, there are typically other function blocks such as central processing units, digital signal processors, custom logic blocks, and large volatile or non-volatile memory blocks. In some cases, the programmable logic block may be a minority of the total central core circuitry.
An end user's PLD design is typically implemented by use of a computer program product (also known as software or, more specifically, design software) produced by the PLD manufacturer and distributed by means of a computer-readable medium such as providing a CD-ROM to the end user or making the design software downloadable over the internet. Typically the manufacturer supplies a library of design elements (also known as library elements) as part of the computer program product. The library design elements provide a layer of insulation between the end user and the circuit details of the programmable elements, control elements, and the other PLD features available to the end user. This makes the design software easier to use for the end user and simplifies the manufacturer's task of processing the end user's complete design by the various tools in the design software.
Library elements can range from the very general to the very specific. An example of a general library element would be a logic module that maps to a programmable element capable of doing any Boolean function of up to four variables depending on the settings of the underlying control elements. When using such a library element, the end user would need to specify the desired Boolean function.
A first example of a specific library element would be a non-varying Boolean function requiring several logic modules to implement. A second example of a specific library element would be an interface to a particular piece of physical hardware. Such a library element could allow the end user to specify a complex functional block like a hardwired, dedicated digital multiplier present on the PLD as part of his design. A third example of a specific library element would be an interface to some aspect of the PLD control logic that would not ordinarily be accessible as part of an end user's pure logic design.
The design software typically provides one or more methods for the end user to specify the necessary design elements to obtain the desired functionality. Typically the user will enter schematics, describe the design in a hardware description language such as Verilog or VHDL, or use some combination thereof. In the case of large, complicated designs, a hierarchy of ever more complex design elements will be built up until the desired functionality is completely described. Then one or more software tools will process the complete design and map the design elements into the programmable elements in the PLD. Then the control data structure necessary for controlling the programmable elements by means of the associated control elements is generated. The method for applying the control data structure to the control elements can vary widely due to both the technology employed, the hardware present on the data processing system running the design software, and design choices made by the end user.
In recent years as integrated circuit process geometries have shrunk into the deep sub-micron range, power consumption has become an increasingly greater problem. This is particularly true in hand-held applications where battery lifetime is of critical importance. Thus PLD manufacturers have started adapting their parts to consume less power. One technique used is to have a low-power mode which is controlled by means of an external low-power mode enable input. This allows the end user's electronic system to place the PLD into low-power mode whenever the functionality implemented in its programmable elements is not needed, thus saving most of the power it would otherwise consume in its normal operating mode. The exact details of power-down mode differ from manufacturer to manufacturer, but most take precautions like blocking or disabling the input buffers to control unnecessary internal switching in response to signal activity on external conductive traces, placing the output buffers into a safe state with respect to the external system, and disabling or placing into a safe state various other features when a signal coupled to the low-power enable input is asserted.
An undesirable aspect of prior art solutions is that the PLD is placed into low-power mode without any regard to the internal state of the end user's design. It is important in many applications to stop the PLD in a deterministic logic state before entering low-power mode. This allows the PLD to resume operation in the exact configuration it was in upon leaving low-power mode. With previous solutions, there is no guarantee that when the low-power enable input is asserted that the logic will stop in a deterministic state.
Users typically work around this problem by placing the PLD internal logic into a deterministic state by means of some external control logic and only then asserting the low-power mode enable input. This requires the use of at least one additional input to the PLD and some knowledge at the system design level of the necessary steps and required timing needed to prepare for a safe assertion of the low-power enable input. This complicates the design of the end user's entire electronic system. Thus, it is highly desirable to have a PLD device that is capable of placing its own internal logic into a deterministic logic state in a manner specified by the end user as part of the complete design programmed into the PLD before placing itself into low-power mode under the control of a single low-power enable input.